Several trends presently exist in the semiconductor device fabrication industry and in the electronics industry. Devices are continually getting smaller, faster and requiring less power, while simultaneously being able to support a greater number of increasingly complex and sophisticated applications. One reason for these trends is that there is an ever increasing demand for small, portable and multifunctional electronic devices. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. These devices rely on one or more small batteries, which are generally rechargeable, as a power source and also require an ever increasing computational and storage capacity to store and process data, such as digital audio, digital video, contact information, database data and the like. In light of all these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, that are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer, for example.
The process of manufacturing integrated circuits typically consists of more than a hundred steps, during which hundreds or thousands of copies of an integrated circuit can be formed on a single wafer. Throughout the process, the wafer has layer after layer of material applied thereto and treated in some fashion to create electrically active regions in and on the semiconductor wafer surface. In MOS transistors, for example, a gate structure containing one or more conductive materials is created from one or more layers, and this gate structure can be energized by applying a voltage thereto to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region on either side of the channel. The source and drain regions facilitate this conductance by virtue of containing a majority of positive (p-type) or negative (n-type) dopant atoms.
Dopant atoms are implanted into the source and drain regions to establish the n or p type regions. It can be appreciated that dopant atoms may, at times, have to be implanted through one or more layers of material to establish the source and drain regions, and that the composition of such layers may slow down or otherwise affect the trajectory of the dopant atoms. Accordingly, if the layers are not substantially uniform, the implanted areas may differ across the wafer resulting in devices having different operating characteristics. Thus, it would be desirable to have substantially uniform layers where dopant atoms are implanted through the layers. However, with conventional processing, and in particular processing to form sidewall spacers adjacent to gate structures, layers are often damaged or otherwise made non-uniform by some of the steps within the process. Such sidewall spacers serve to direct dopant atoms into certain ‘implant’ regions within the substrate and are formed, in part, by etching a layer of material overlying the gate structures. The etchant utilized, however, can also etch or ‘eat away’ some of the layer(s) adjacent to the gate structures, making them non-uniform and thus adversely affecting the implantation process. Thus, it would be desirable to form sidewall spacers while maintaining the uniformity of adjacent layers.
Also, patterning or otherwise processing some layers in conventional manners can lead to undesirable channeling that can short out conductive areas, such as electrical contacts for source and drain regions, for example. Such channeling is more prone to occur between features that are formed very close to one another, such as between sidewall spacers that are continually formed closer to one another as scaling continues. By way of example, a relatively thin layer of oxide material that overlies gate structures, sidewall spacers and other areas of the wafer may be non-uniform due to limitations associated with tools available and/or process variations. Accordingly, such a layer may have to be etched, stripped or otherwise removed from the wafer. Doing so, however, may cause a small channel to be formed in an underlying layer (e.g., a shallow trench isolation (STI) layer) that electrically isolates two or more conductive areas from one another. The channel can thus electrically couple the conductive areas, particularly where a material, such as tungsten (W), for example, is subsequently applied in the fabrication process. The material can diffuse into the channel and electrically couple and short out the conductive areas. Thus, it would be desirable to establish uniform layers in a manner that does not facilitate shorting out conductive areas.
Additionally, it is at times desirable to protect or ‘block off’ portions of material from subsequent processing. For example, certain layers of material can be salicided or treated to become (more) electrically conductive and/or to establish areas where electrical contacts of connections can be made. It may, however, be desirable to protect some regions from such treatment(s) so that such regions remain ‘resistive’ or non-conductive. Conventionally, additional steps are required to isolate or protect such regions from subsequent processing. As with most fabrication processing, however, it is an ongoing desire to simplify the process and reduce the time, material and equipment required to fabricate semiconductor devices. Accordingly, it would be desirable to perform a salicide blocking process in a more efficient manner.
Further, as device sizes continue to shrink, the close proximity of certain areas can lead to undesirable results. With regard to transistors, for example, forming source and drain regions too close to the gate structure can lead to diffusion or migration of source/drain dopants into the channel region under the gate structure, which can in turn lead to skewed threshold voltages, leakage currents, etc., all of which are undesirable. Additionally, certain design rules come into play as scaling occurs. Such design rules set forth maximum and/or minimum allowable values for certain dimensions, for example. One such design rule may, for example, dictate a maximum allowable distance between a gate structure and a source contact. However, satisfying this design rule with conventional fabrication techniques may not be feasible since forming the source region very close to the gate structure may allow source dopants to drift into the channel.